Generally, analog switching circuits comprise a plurality of parallel connected switches which couple a plurality of analog voltages to an interface circuit. The interface circuit may be coupled to a digital circuit having devices requiring low threshold voltages for high performance. A common source of error is caused by those analog switches which are disabled and which conduct a leakage current. A conventional CMOS analog switch comprises as a minimum two transistors of opposite conductivity type. The leakage currents result primarily from the transistors of the analog switch also having a low or normal threshold voltage. Due to process expediency, the threshold voltages of the transistors of the parallel coupled analog switches are typically the same as the threshold voltages of transistors in the interface and digital circuits. A partial solution to the leakage current problem has been to make the threshold voltage of all the transistors sufficiently high to prevent leakage. However, this is often unsatisfactory for high performance digital circuitry. An NMOS process which uses multiple implants to achieve multiple threshold voltages for preselected devices is shown in U.S. Pat. No. 4,033,026 to Pashley. However, the numerous process steps described therein often makes selective implanting undesirable.